μeffCox
2
⋅ eq
Once upon a time, using a square law type of MOS transistor model was sufficient to kind of accurately model transistor behavior. That was is the era where layouts were made using scissors and tape.
Nowadays, quite simple MOS transistor models can be used for calculations by hand and for back-of-envelope calculations.As such they can provide some insight and they can be used to do very coarse dimensioning of MOS transistors. Just for completeness sake, some hand-derivation-suited equations are listed below. In nowadays technologies, second order effects are that significant that for accurate results these equations are not suited.
For the back-of-the-envelope relations and optimizations below, and also for the notations in ProMOST, the following notation conventions are used:
Simplified current-voltage relations for (N-type) MOS transistors are shown below. Here the textbook distinction between strong inversion and weak inversion is made, while in strong inversion operating in saturation and in the linear (triode) region is shown. For P-type devices, the relations are the same except for many ”-”-signs.
| iD = μeffCox2 | (strong inversion, saturation) | |||||
| iD = μeffCox | (strong inversion, linear region) | |||||
| iD = ID0 ⋅ ⋅ eq
| (weak inversion, forward active) |
Frequently, the shorthand vGT is used for effective gate overdrive voltage (vGS − V T ). Glueing
together the strong inversion and weak inversion can be done by lower-limiting V GT to
V GTmin = 2 ⋅ n ⋅
. A more smooth way is using a (mos9, bsim3, bsim4 style) glue function.
As reported in [1], conventional MOS models such as MOS Model 9 and BSIM4 are
threshold-voltage-based models, which make use of approximate expressions of the
drain-source channel current iDS in the weak-inversion region (i.e., subthreshold) and in
the strong-inversion region (i.e., well above threshold). These approximate equations
are tied together using a mathematical smoothing function, resulting in neither a
physical nor an accurate description of iDS in the moderate inversion region (i.e., around
threshold). With the constant downscaling of supply voltage the moderate inversion region
becomes more and more important, and an accurate description of this region is thus
essential.
The more accurate surface potental based models (BSIM6, BSIMIMG [2], PSP, MOS11) do not lend themselves for hand calculations.
From the very much simplified voltage-current equations above it readily follows that the transconductance of the MOS transistor is:
In strong inversion, saturation:
| gm | = μeffCox ⋅ V GT | ||
=  | |||
=  |
These three forms are the same but allow to derive or set the transistor’s transconductance in three different ways (or with different constraints). In strong inversion, triode and in weak inversion the transconductance is respectively
gm = μeffCox ⋅ V DS | |||
gm =  ID |
The factor n typically is 1.2...1.4 in bulk CMOS technologies and close to 1.0 in multigate and in UTB technologies.
Assuming the idealized element equations above, the drain conductance of the transistors in saturation is 0 [S]. To get a more realistic estimation, the element equations are a little extended below, including an ”Early voltage” dependency:
iD =  μeffCox  2 ⋅ (1 + λ ⋅ v
DS) | (strong inversion, saturation) | |||||
iD = μeffCox ⋅ | (strong inversion, linear region) | |||||
iD = ID0 ⋅ ⋅ eq
⋅ (1 + λ ⋅ vDS) | (weak inversion, forward active) |
Then the drain conductance of the MOS transistor is:
| gds = λID | (strong inversion, saturation) | |||||
gds = μeffCox (V GT − V DS) | (strong inversion, linear region) | |||||
| gds = λID | (weak inversion, forward active) |
Drain conductance in strong inversion saturation is due to a number of effects, including channel length modulation, DIBL, mobility reduction effects and much more. Except for operation in the linear region, there is no simple relation for drain conductance suitable for hand calculations when including device scaling (for constrained optimizations) or harmonic content.
The unity gain frequency of a MOS transistor is the frequency at which the (small signal) gate current equals the (small signal) drain current into a low ohmic load. The capacitance at the gate-source port is the sum of the overlap capacitances and the cgg ≡ ∂Qg∕∂vg. In strong inversion the gate charge is due to the (about constant) depletion charge and the inversion charge. Neglecting the overlap capacitances for the back-of-the envelope estimations and assuming that the inversion charge is located at either side of the gate oxide/
In strong inversion, saturation
cgg ≈ CoxWL | |||
ig = vgs ⋅ 2π ⋅ f ⋅ CoxWL | |||
| id = vgs ⋅ gm |
which yields
In weak inversion, the inversion charge is low and can be neglected for the transistor’s cgg. Then the transistor’s gate capacitance consists of overlap capacitances and the intrinsic cgg that is due to the (here gate voltage dependent) depletion charge. This voltage dependent depletion charge also results in the ideality factor n for the iD(vGS)-relation in weak inversion and is very much related to the body effect of the transistor.
Being too complex for a generic equation for back-of-the-envelop derivations, no equation for weak inversion cgg and fUG is provided here. As a rule of thumb, in weak inversion cgg ≈ CoxWL ⋅ gmb,si∕gm,si. In simple models the cgg is only a weak function of vGS in weak inversion and steps to its strong inversion value at vGS = V T .
Following a (simplified) Pelgrom law, the threshold voltage V T and the current factor μeffCox of an MOS transistor spread. Simplified, these can be described as
σV T =  | |||
σβ = β ⋅ |
where AV T is about 1mV∕nm ⋅ μm where the ”nm” is the gate oxide thickness for the
transistor expressed in [nm], and where Aβ
0.01. This translates into
 =  ⋅ 2 +  | |||
σΔID2 =  ⋅ 2 + I
D2 ⋅ | |||
σvgs2 =  +  ⋅ 2 |
Thermal noise occurs in any conductive material. For linear resistors it is Si = in,eff2 = 4kT ⋅
⋅BW
for an equivalent parallel noise current source (Norton equivalent) or alternatively
Sv = vn,eff2 = 4kT ⋅R ⋅BW for a series equivalent noise voltage source (Thevenin equivalent).
In this, BW is the equivalent noise bandwidth. In idealized MOS transistors thermal noise
occurs only in the channel and can be related to the transistor’s gm, gds or ID when
including a noise factor γ that takes into account the impact of non-linear behavior of the
transistor on the noise. Then for the output referred noise (in parallel to the drain-source
port):
Si = in,eff2 =  ⋅ 4kT ⋅ gm ⋅ BW | (strong inversion, saturation) | |||||
Si = in,eff2 = γ ⋅ 4kT ⋅ ( gm + gds) ⋅ BW | (strong inversion, linear region) | |||||
| Si = in,eff2 = 2q ⋅ I D ⋅ BW | (weak inversion, forward active) |
The noise factor γ is 1 far in triode and approaches 
towards saturation. This output (current)
referred noise can be rewritten into an equivalent input referred noise source in series with the
gate voltage:
Sv = vn,eff2 =  ⋅ 4kT ⋅ ⋅ BW | (strong inversion, saturation) | |||||
Sv = vn,eff2 = γ ⋅ 4kT ⋅ ⋅ ⋅ BW | (strong inversion, linear region) | |||||
Sv = vn,eff2 = 2nkT ⋅ ⋅ BW | (weak inversion, forward active) |
There are many equations for flicker noise in transistors, among other due to the fact that there are various descriptions or mechanisms for this type of noise. In all cases, the noise power density decreases as 1∕f. One of the widely used simple relations is
Si = 
where 0.5 ≤ AF ≤ 2 (technology and bias dependent) and where Kf is
technology dependent.
Nowaday, effects such as DIBL, mobility reduction, velocity saturation, SCE, gate depletion and more cause significant deviations from the square law I-V-relations. Below, a short treaty of only the impact of mobility reduction and velocity saturation is given. Aiming at equations that can be used in hand calculation, the description and analysis are quite significantly simplified. Current transistor models can quite accurately model these effects but are not suited at all for hand derivations.
The mobility parameter μeff in e.g. the equations for drain current is the effective mobility for the carriers in the inversion layer, for the applied vertical and lateral field. The vertical field is due to both the depletion charge and due to the inversion charge which is about proportional to vGS. The vertical field in the inversion layer is typically modelled proportional to the voltage drop acroos =this inversion layer, which is about vGS − V T . Simplified, the effective carrier mobility μeff can be modelled as a low-field mobility μ0 decreased by terms that model the mobility reduction due to the vertical and lateral field:
μeff = μ0 ⋅ ⋅ . |
In this equation, Esat is the lateral field in the inversion layer at which the carrier velocity of charge carriers in the inversion layer starts to saturate. Now, for (very short) transistors operated such that L ⋅ Esat ≪ vGS − V T ,
| iD | =  ⋅ ⋅ Cox  2 | ||
=  WEsatμ′C
ox  | |||
= WvsatCox | |||
| gm | = WvsatCox |
where the customary Esat = 2vsat∕μ is used; in silicon, vsat for electrons is around 107 cm/s. Note the linear relation between iD and vGS in this region of operation and note the vGS-independent gm.
The equations in this chapter are suited for hand derivations, to get some insight. Period. Hence they are very useful to understand your circuit, to do very coarse dimensioning.
If you want any accuracy, do not use them. Many effects that result in deviation from the idealized equations are quite important in modern CMOS technologies. This includes — and by no means is limited to — short channel effects, mobility reduction effects and stress induced property changes. If you want decent to good accuracy, you have to use state-of-the-art transistor models. These have up to many hundreds of model parameters, and there is a reason for that: accuracy.