5 Transcapacitances and transconductances

The vast majority of transistor models define terminal currents and terminal charges as shown in Figure 8.

pict

Figure 8:A MOS transistor with conventional voltage, current and charge definitions

Being inherently a four-terminal device, four generic equations for the current follow:

iD (vD,  vG, vS, vB )
iG (vD, vG, vS, vB )

 iS(vD, vG, vS, vB )
iB (vD, vG, vS, vB )

and four generic equations for terminal charge follow:

qD (vD, vG, vS, vB )
q  (v  , v , v , v )
 G  D    G   S  B
qS (vD, vG, vS, vB )
qB (vD,  vG, vS, vB )

Small-signal wise this leads to 16 transconductances

      dix-
gxy = dvy     x,y ∈ {D, G, S,B }

and leads to 16 transcapacitances

      dqx
cxy = ----    x,y ∈ {D, G, S,B }
      dvy

These gxy and cxy can be collected in 16 Y-parameters as Yxy = gxy + jωcxy.

5.1 Symmetry leading to 16=9...

Note that no properties, no currents, nothing in the behavior of a transistor change if all terminal voltages are changed by an arbitrary ΔV . Offsetting all terminal voltages by the same amount effectively only means that your reference voltage is changed. And your transistor does not care what you assume as reference potential. This implies that:

5.2 Symmetry leading to negative gxy-s and negative cxy-s

The fact that adding the same voltage to all nodes does not change the behavior of the transistor in any way, implies that the sum of some transcapacitances and transconductances is zero:

  ∑
        gxy = 0
y∈D,G,S,B
  ∑
        cxy = 0
y∈D,G,S,B

while the laws of conservation of charge enforce other sums to zero:

  ∑
        gxy = 0
x∈D,G,S,B
  ∑     c   = 0
x∈D,G,S,B xy

The fact that these sums equal zero implies that a number of the 16 transcapacitances and transconductances have negative values.

Although e.g. negative transcapacitances may seem weird at first sight, it only means that the charge at some node decreases if the voltage at one of the (other) nodes increases. To illustrate that this is normal behavior of even passive (linear, two terminal) devices, the example below assumes a regular capacitor.

pict

Figure 9:A capacitor

Applying voltages vt and vb to the top plate and bottom plate respectively, charge accumulates on the top plate (indicated by “t”) and on the bottom plate (indicated by “b”) as

qt(vt,vb)  = C ⋅(vt,cb)
q (v,v )  = − C ⋅(v,c )
 b  t b            t b

which leads to

      dqt            dqt
 ctt = dvt = C  ctb = dvb = − C
                      dq
cbt = dqdvbt-= − C  cbb =---b= C
                     dvb

It may be clear that in this set of four transcapacitances — associated with a straight-forward linear capacitor — also shows the redundancy properties and the summing-to-zero properties that were described above. Using those, we usually describe the linear capacitor by its ctt = C or by its cbb = C in hand derivations and manual calculations. Similar results follow for two-terminal resistive component, or for any generic 2 terminal device for that matter. Moreover, devices with more-than-2 ports are merely extensions of the 2-terminal devices.

5.3 Hey, there’s a cgs and a csg with a different value...

For a device with 2 terminals, the laws of conservation of charge (per unit time for currents) dictates a very simple symmetry. For e.g. resistors and capacitors

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Figure 10:A capacitor and a resistor

it can readily be derived that the transcapacitances respectively transconductances are:

                     dq
 ctt = ddqvtt = C  ctb =--t = − C
                     dvb
c  =  dqb-= − C  c  = -dqb= C
 bt   dvt         bb  dvb
 gtt = dit=  1-  gtb = dit = − 1-
      dvt   R        dvb     R
     dib     1-      -dib   -1
gbt = dvt = − R gbb = dvb = R

For two-terminal devices, gxy = gyx and cxy = cyx.

For devices with more than 2 terminals, in general gxy≠gyx and cxy≠cyx. For example a transcapacitance cgd in general is not equal to cdg: the change in (here) gate charge qG(V D,V G,V S,V B) due to a drain voltage change can be completely different from the change in drain charge qD(V D,V G,V S,V B) due to a gate voltage change. The same holds of course any transcapacitance cxy and cyx for all x≠y, and for any gxy and gyx for all x≠y: in general they are not identical. Only in special cases — like 2-terminal devices — they have to be identical.