As a circuit designer, you have to optimize circuit topologies. As circuit designer, you have to identify bottlenecks and solve them. In this, you can take many roles: reactive, proactive or being in charge.
My suggestion would be to be in charge. Let the circuit and all transistors in it do what you want them to do. Just enforce individual and collective behavior. I know that that sounds quite harsh but as of yet no transistor filed a complaint to me; just do not cross the limits. And if they cannot reach your target performance, then you automatically get pretty good hints where it goes wrong. Then you know where you have to fix things, where you may have to change the type of transistor or where you have to change the circuit topology. Being in charge is by far the most efficient way of designing.
A reactive or pro-reactive attitude can also be done, but it takes quite a lot more effort and
is much less fun. For this designer attitude, just grab some initial bias settings and
dimensions, fire up the circuit simulator and examine the collective behavior of all your
subordinates, aka your transistors. Tweak and re-run and tweak and re-run and ... In
this case the 3N-dimensional problem is really a problem, as described in section
2.2.
Just be in charge of your design.